SC16 Emerging Technology Booth

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We’ll have a booth at SC16 Emerging Technology area. Please drop by!

You can find a PDF of our poster below here.


Motivation

The idea of SoCs is starting to be applied to HPC, building chips from IP building blocks.

soc

Commercial, closed-source IP is a major drag on innovation in all technology spaces. Open-source hardware has the potential to ignite multiple paths in the semiconductor industry: increasing diversity by driving costs down, lowering the barrier to entry, and opening the door for customization.

New companies are being founded based on open source.

riscv-companies


Goal

Using pre-verified open source IP, we want to create an open source silicon chip complete with a full software toolchain, including specialized instructions.


Hardware Architecture

Tiled Architecture
Each tile will contain the open source RISC-V based Rocket core with a custom Personal Meamory Engine (PME), connected to an OpenSoC Fabric network.
tile
Configurable Network
The tiles will be arranged in a mesh networking using the open source OpenSoC Fabric, with a node for a connection to main memory and off-chip communication.
network

Software Infrastructure

Programming Models
The programming model relies on a MIMD approach where a single host (x86_64) application will launch multiple RISC-V threads. Each RISC-V thread may have additional, extended instruction support for application-specific computing workloads.
progmodel
Compiler & Tool Chain
The compiler/tool chain will be based upon LLVM. The initial support will include C, C++ and, ObjectiveC source compilation using the RISC-V LLVM target. In addition to basic RISC-V support, the environment will also provide auto-generated instruction, register and inline intrinsic extensions for application-specific architecture support.
compiler
Execution Environment
The execution environment provides execution/debugging capabilities using an abstract set of interfaces. The OHPCRUN tool provides the ability to initiate application workloads on the device as well as provide a messaging interface for client debuggers to interact with an active workload. The LLVM LLDB client debugger also will be utilized.
execenv

Acknowledgements

We’d like to acknowledge the Laboratory for Physical Science and the Department of Energy for helping fund this work.